About the Company

Avaron AB is a growing consultancy focused on technology, finance, and business support. We match your expertise with the market's most interesting assignments, offering a platform where your professional development is central.

About the Assignment

We are looking for a Senior ASIC Designer to take technical ownership in advanced ASIC/SoC development. You will work end-to-end from specification and architecture to tape-out and bring-up, collaborating closely with design, verification, physical design, firmware, and software teams. The environment is hands-on and engineering-driven, with a focus on performance, quality, and reliable delivery.

Job Description

• Own and deliver ASIC/SoC blocks and subsystems from specification to tape-out and bring-up
• Define microarchitecture and write/maintain design specifications and interface control documentation (ICDs)
• Design and implement RTL in Verilog/SystemVerilog
• Collaborate with verification teams on test planning, assertions, and coverage
• Work with synthesis and timing closure, including constraints (SDC) and analysis in PrimeTime
• Guide and align with physical design teams regarding floorplanning considerations, congestion, and timing paths
• Perform chip-level integration work, including interfaces and protocols (e.g., AXI, PCIe, Ethernet)
• Contribute to power/performance/area (PPA) trade-offs and low-power design approaches (e.g., power domains, clock gating, DVFS)
• Support collaboration with DFT teams around scan/MBIST/boundary scan topics
• Build and use models for system-level or performance evaluation (e.g., Python, C/C++, SystemC)
• Automate design and flow tasks using scripting
• Mentor engineers and review designs to ensure quality and consistency

Requirements

• 8–15+ years of experience in ASIC/SoC design and development
• Proven ownership of multiple ASIC projects from specification to tape-out and bring-up
• Expert proficiency in Verilog/SystemVerilog for RTL design
• Experience developing microarchitecture specifications for complex subsystems
• Understanding of clocking, resets, power domains, FSMs, pipelining, and parallelism
• Working knowledge of functional verification methodologies (SystemVerilog, UVM)
• Familiarity with simulators such as VCS, Questa, or ModelSim
• Hands-on experience with synthesis tools such as Synopsys Design Compiler or Cadence Genus
• Ability to define timing constraints (SDC) and drive timing closure using PrimeTime
• Experience producing architectural specifications, ICDs, and design guides
• Knowledge of low-power concepts and standards such as UPF/CPF, clock gating, power domains, and DVFS
• Familiarity with DFT techniques such as scan chains, MBIST, and boundary scan
• Experience with performance modeling using Python, C/C++, or SystemC
• Proficiency in Python, Perl, or Tcl for scripting and automation

Nice to have

• Familiarity with High-Level Synthesis (HLS) flows
• Knowledge of AI/ML accelerators, networking, or video processing pipelines
• Experience with multi-die (chiplet) integration and 2.5D/3D packaging
• Understanding of security architectures, encryption modules, or hardware IP protection
• Background in post-silicon validation, lab bring-up, or FPGA prototyping
• Exposure to embedded firmware/software, drivers, or hardware-software co-design

Application

Selections are made on an ongoing basis, so we recommend that you apply as soon as possible.